A 10Gb/s data-dependent jitter equalizer

An equalization circuit is presented that reduces data-dependent jitter by aligning data transition deviations. This paper presents an analytic solution to data-dependent jitter and demonstrates its impact on the phase noise of the recovered clock. A data-dependent jitter equalizer is presented that compensates for impairment of the channel and lowers the phase noise of the recovered clock. The circuit is implemented in a SiGe BiCMOS process and operates at 10 Gb/s. It suppresses phase noise resulting from data-dependent jitter by 10 dB

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

Cancellation of crosstalk-induced jitter

A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre- or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10^sup-12 BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps

Data-dependent jitter and crosstalk-induced bounded uncorrelated jitter in copper interconnects

This paper resolves the jitter impairment of non-return-to-zero data in transmission lines. The limited bandwidth of the transmission line introduces data-dependent jitter. Crosstalk between neighbouring lines results in bounded uncorrelated jitter in the data eye. An analytical approach to representing data-dependent jitter and crosstalk-induced bounded uncorrelated jitter is presented. Comparison with jitter measurements of microstrip lines on FR4 board demonstrated accuracy to within 15% of the predictions for deterministic jitter

Estimating data-dependent jitter of a general LTI system from step response

We present a method for estimating data dependent jitter (DDJ) introduced by a general LTI system, based on the system's step response. A perturbation technique is used to generalize the analytical expression for DDJ. Different scales of DDJ are defined that characterize the probability distribution of jitter. In particular, we identify a dominant prior bit that signifies the well-known distribution of DDJ, the two impulse functions. We also highlight that system bandwidth is not a complete measure for predicting DDJ. We verify our generalized analytical expression of DDJ experimentally and show that estimation errors are less than 7.5%

Shipboard Insurrections, the British Government and Anglo-American Society in the Early 18th Century

Captain Francis Messervy, first time captain on the slave ship Ferrers and perhaps overly ecstatic after his most recent successes at sea, maneuvered unprotected below deck to inspect his newly purchased Africans. As he lurched further down into the Ferrers, Messervy would have seen sailors whose duty it was to guard against insurrection and the three hundred or more Africans he had recently purchased following a war between two neighboring polities near Cetre-Crue. What Messervy perceived as good fortune, fellow captain William Snelgrave saw as cause for concern, noting that controlling many Negroes of one Town and Language had its inherent risks. These suspicions, borne from experience as a slave ship captain, proved correct a few months later when news on the Guinea coast highlighted a large-scale insurrection aboard the Ferrers. Captains and tars alike shared tales of Africans who beat out his [Messervy\u27s] brains with the little Tubs, and ofthe ensuing battle in which nearly eighty Africans died

An Integrated Subharmonic Coupled-Oscillator Scheme for a 60-GHz Phased-Array Transmitter

This paper describes the design of an integrated coupled-oscillator array in SiGe for millimeter-wave applications. The design focuses on a scalable radio architecture where multiple dies are tiled to form larger arrays. A 2 × 2 oscillator array for a 60-GHz transmitter is fabricated with integrated power amplifiers and on-chip antennas. To lock between multiple dies, an injection-locking scheme appropriate for wire-bond interconnects is described. The 2 × 2 array demonstrates a 200–MHz locking range and 1 × 4 array formed by two adjacent chips has a 60-MHz locking range. The phase noise of the coupled oscillators is below 100 dBc/Hz at a 1-MHz offset when locked to an external reference. To the best of the authors’ knowledge, this is the highest frequency demonstration of coupled oscillators fabricated in a conventional silicon integrated-circuit process